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Memorandum 6M~f>780 

Sheet 1 of 15 Sheets 

Division 6 — Lincoln Laboratory 

Massachusetts Institute of Technology 

Lexington 73, Massachusetts 

SUBJECT: SOME EXAMPLES OF TX-2 HiOGRAMMING 

To: Distribution Mst 

From: Ho Philip Peterson 54 « (SSLQyO ^ J^torua^rv v 

Date: July 23,1958 

Approved: V^/}<CL >g 

Abstracts Six short programs are presented here to illustrate many 
of the somewhat inscrutable features of TX-2 programming, 
These programs are called? 

Is A Checkerboard Pattern Generator 

lis The Inehworm 

Ills The Memory Mirror 

IV s An Autocorrelation Program 

Vs The Flexo-Octal Converter 

Vis A Binary Read-in Routine 

Distribution Lists 

Group 63 Staff Fraehtman, Ho E 

Arden, Dean (Barta) Friek, F 

tenw<> J* Grandy, Co 

Attridge, ¥• Hazel, F P e 

Bagley, P Ro Heart, F 

Bailey ^ %* Holmes, lo 

Briscoe, Ho Israel, Do 

Buzzarfc, Bo Mason, Ifeu 

Daggett, No p^ Eo (Servo Labo) 

Dinneen, G P c Rising, Ho K„ 

Dustin, Do E Thomas, Lo Mo 

Forgie, Carma Tritter, A L G 

Vance, R e R e 2raket, Co Ao 

Ku^fffi? 5 M S£ 1 .L ha L b ?T P n Par 5 J f0 f IS 1 ^"? 1 USe on i y - J 1 ¥* n( * been reviewed 2 - The research reported in this document was 

rKsw stems s ttiBnuinss 



9 



6K-5780 i 

BTOODUCTORy REMARKS 

3!he six example programs presented in this paper illustrate many of 
the somewhat inscrutable features of TX-2 programming « A few assumptions 
however have been made by the author about the reader These assumptions 
are: 

1) that the reader knows how to program! 

2} that the reader is familiar with TX=2 nomenclatures (this 

familiarity may be attained by studying ®The Lincoln TX~2 

Computer," (6M»1*%8)| and 
3) that the reader has a copy of w The TX-2 Programmer's Guide* 1 

for reference (6M~£807)<> 

NOTATION 

The code part of each instruction is written as a group of 3 capital 
letters (ADD, JMP, etc G )o Any superscript numbers preceding the code 
part refer to a configuration memory location, except for JPI, JNX, JMP 
and SKM instructions * Superscript numbers following a code refer to an 
index memory location except for SKM type instructions where this is the 
number of the bit in the addressed wordo lower case numbers following a 
code are main memory addresses o 

A colon means "hold control until the next instruction,^ Brackets 
mean «defer the address* 1 and imply that bit 2<>9 of the address is a 0NE o 
lower case letters are hopefully self -explanatory 

To the left of many instructions will be an explanatory notation 
using four little lines which show the permutation involved by how they 
cross | the active quarters of central machine registers by arrowheads, 
and 5 when necessary, the fracture (or coupling or subwords) by little 
cups a This configuration will be specified by the contents of the indi- 
cated configuration memory wordo 

A number or word followed by "slash equals* defines the address of 
the instruction or constant to the right of it* A word followed by 
^equals slash 8 * is the name of the register following * 

An address section with a large L prefixing it, as in 763 of I>rogram I< 
means the address of M a register containing what is indicated. 11 

All numbers in programs are octal unless otherwise indicated* Numbers 
are punctuated witk commas separating the meaningful portions of the whole 
36 bit wordo A single comma separates 9 bit (3 octal digit) quarters when 
the word is dealt with in quarters Two consecutive £oiraias will separate 
the word into 18 bit (6 octal digit) pieces o 



6M-5780 



Io A Checkerboard Pattern Generator 
The Problem 



When a core memory is being checked for operating margins 9 a 
"bad* pattern of OKBS and ZEH0S is desired (see Engineering Note 
E-ii88)o One of the worst conditions starts with a checkerboard 
pattern which looks like this in each memory plane: 



110 11 
10 110 
10 110 
110 11 
110 11 



oooooooooo 
o ooo oooooo 
oooopooooo 



The complement of this pattern is also a checkerboard <, The addresses 
increase from left to right and top to bottom beginning with address 
000 at the upper lefto In the case of a 2$6 2 memory plane,, it takes 
8 bits to address a row or a column (16 address bits in all)* 

If one computes the parity of the two least significant bits of 
the row address and the two least significant bits of the column 
address,, one will find that if the parity of these four bits is odd,, 
a OHE will be at that address | if even $ a ZERO will be there* 

The problem is to construct a program which generates this pattern 
in aH 65^536 bits of each memory plane The program must fit into 
the 16 toggle switch registers o 

The Solution 

Program I generates the checkerboard pattern by using four SK2 
instructions to look at the two sets of least-significant address bitSo 
These bits are 1.1, 1 2, 1 Q and 2ol<> iben any one of them is a tm, 
the SE2 doesn't skip and an MKC is executed which complements bit 3*1 
of the E register o After examining the four address bits., E register 
bit 3ol will be ZEE0 for an even parity or ONE for an odd parity 
The whole address is kept in index register 1 and the DPT at ?£l* puts 
the address in the right half of the E register P leaving the left half 
all ZEROS since configuration is useda After computing the parity^ 
the left half of E is put in index register 2 and the IDE at 763* puts 
the word at 766 in E if the parity is eren 9 or the word at ?6? if it 
is oddo The word in E is stored away at the address and the address 
is counted down* The address was reset by the ESI in 750 to 177 777o 
This number is kept in the A register (377*71*0) which is being simu»° 
lated by a toggle switch register as of this writingo 

#The three most significant octal digits of addresses (377 in toggle switch 
addresses) will be omitted for brevity »s sake* 



6M-5780 



OCTAL EQUIVALENT 

02 11 01 377,7*0 

00 16 01 377,7** 

10 17 *1 377,' 

03 17 61 377/ 
10 17 31 377 , 
03 17 61 377 , 
10 17 22 377, 
03 17 61 377, 
10 17 21 377,7** 
03 17 61 377, 
02 11 02 377i 



00 20 02 377*766 



00 30 01 000 5 000 



36 06 01 377,751 



00 05 00 377,750 



77 72 77 *00 027 



ADDRESS 
377 750 

751 

752 



756 

757 

377 760 

761 



766 
767 



l /3jjK, 2RSXl L!77*777«-| 



SKZ 2 * 1 a 



s*\ 



SKZ X » 9 e reg= 



s*x 



SKZ 1 * 2 e reg. 



3, 1 



SKZ 1 * 1 e reg. 



s m x 



2oov2 



^* ■* t 



\1 



763 1 1 1 J ° ldeS Ls? 



1 I 1 1 °STE 1 memory 



Rrogram I A Checkerboard Pattern Generator 



6M-5780 3a- 

OCTAL EQUIVALENT ADDRESS SYMBOLIC 

02 11 01 377,7*0 377 750 ^^ 2r SX x |_177,777«- 

00 16 01 377,7** 751 \j j -l, <l, ^PX 1 e reg<_, 

10 17 41 377,7** 752 SKZ 2 * 1 e reg-, 

i 

03 17 61 377,744 753 MKC 3 ' 1 e reg! 

I 

J 
10 17 31 377,74* 75* SKZ 1 * 9 e reg", 

I 
03 17 61377,7** 755 MKC 3 ' 1 e reg | 

10 17 22 377,7** 756 SKZ 1 ' 2 e reg., 

03 17 61 377,7*4 757 MKC 3 - 1 e reg | 

10 17 21 377,7** 377 760 SKZ 1 * 1 e reg^ 

l 
03 17 61 377,7** 761 MKC 3 - 1 e reg I 

I 

02 11 02 377,7** 762 >5$C S RSX 2 e reg 1 ^ 

00 20 02 377,766 763 a a ° ldez i_w ord 

00 30 01 000,000 76* 1 1 1 1 "STE 1 memory 
36 06 01 377,751 765 ^JPX 1 next 



00 05 00 377,750 766 (word) JMP restart 

77 72 77 *00 027 767 (- word) 

Program I A Checkerboard Pattern Generator 



6M-5780 i 9 

Note that the word stored away for even parity is the JHP instruc- 
tion at 766 which restarts the process after the address has been 
counted down through OGO* If one wishes to write the pattern just 
once* put ALL ZEROS in ?66 and ALL OSES in 767 . tt-2 will halt with 
an illegal instruction alarm (ICSAL) if it tries to execute an instruc- 
tion with 00 as the operation code* Suiting *0 in 766 and -0 in 767 
has the advantage that the checkerboard patterns in each digit plane 
will be identical* 

Exercises To Prove To Yourself That You Really Understand 

3y changing a single toggle switch* the checkerboard pattern will 
be complemented. SJhich switch? (Hints any one or three of four will 
dOo) 

What would you do to put the pattern just in the lower addressed 
half of memory? Upper half? Middle quarter? 

Two memory planes of the 38 will not have a checkerboard pattern 
in them* They are the parity bit plane and the meta bit (lulO) plane • 
what program changes will put the pattern in either plane? (Notes 
only an SKM can modify a meta bit*) 



6M-5780 £o 

Ho The Inchvorm 
The Problem 

A classical programming exercise is to design a routine which 
will move itself along through memory 5, carrying with it as it goes 
all necessary constants for repeating this "inchworm" process « The 
program for starting the inch worm on its way must fit into TX~2 ff s 
16 toggle switch storage registers , naturallyo 

The Solution 

Program II solves the problem by storing in registers 001 - 00? 
the program shown<> This program in 001 - 007 then forms the one in 
010 - 016 ifcich duplicates itself in 01? - 025 and so one The pro- 
gram in togs works like the ones in main memory except for a few 
special setting up instructions „ 

The SPF instruction in 752 specifies that configuration 3k will 
permute quarter 3 into quarter 1 and extend its sign into quarter 2 Q 
The RSX in 755* 1, 10, etc uses this oddball configuration to reset 
index register 71 to a =6 from quarter 3 of registers 762 s 6, l$ s etc. 
This trick allows the inchworm program to avoid carrying constants 
per se along with it « Each »old» inchworm setment can simply ^fall 81 
into the newly formed one without jumping around some constants 

Index register 2 contains the constant necessary for the program 
to move itself into the next location. When moving from togs to 
core memory 9 this constant is i*00 023 and the HSX in 753 fixes it up 
when moving on in core memory, this constant is 000,007 and the RSX 
in 764 sets it up<> 

The ESX in 75ii resets index register 3 to snap back to togs after 
the last address desired is reachedo For illustrative purposes the 
address constant 577*760 was chosen* Since the JPX in 763, 7, 16 
etco jumps when the index register is positive, for our purposes it 
must be negative until the end is reachedo Consequently 1*00,000 is 
added to 177.760 and that number (577,760) is set up in left half of 
750» Each time an inchworm ^segment* is executed,, the corresponding 
JFX will subtract 7 from the contents of index register 3* When con- 
trol gets to the segment in 177,757 - 766, index register 3 will have 
become positive and control will be transferred to togs (after a seg- 
ment is written into 177,767 to 75) starting the process over againo 

The routine in 755 to 763 maps itself into 000 to 007, preserving 
the address parts of the instructions in 757, 760 and 763 as they go 

*u °?& °^' *?? °° 7 ^ the action Gf thQ Sm in 7*7 *ich skips over 
the AEX when bxt 3o2 of a word is a 0N£ o These three invariant 
instructions refer to fixed locations so they must not be changed 
by the &DX as the other four are c Bit 3*2 was arranged to be ONE in 
the invariant instructions and ZERO in the variable instructions o 



OCTAL EQUIVALENT 

577 760, ,400 023 

362 

34 21 00 377*751 

01 11 02 377*750 

02 11 03 377*750 
74 11 71 377,762 

40 20 71 377,763 
54 17 62 377, 

41 15 02 377/ 

40 30 71 000,007 

41 771 377*756 
70 06 03 377*752 
41 11 02 377*761 



01 30 00 000,005 
00 05 00 000,001 



ADDRESS 

377 750 

751 



753 



755 



377 760 



762 



764 



6M-5780 



>* * 



conflg 34 set up 



3«f 



„ 1 L I I, 1 hsx- 8 

^SSSu 2RSX3 

;>^<^ / s 34 RSX^377*762 

1 i I I': ° T ™ ?Ti 



I U I. 



3*2, 



2 



Ull-. STE T1 000,007 



■T 



IIU : lRSx2 

I LI i, x *™" 

J I J, 4, x i 



001 


; a4 RSX T1 6 


2 


% LDE TX ' 7 


3 


1 SKN 3 « 2 37 


4 


% *ADX a 377 


5 


s °STE T1 16 


6 


s^JNX 71 2 


7 


s~ 7 JPX 3 377. 



4doy^1 



a o2377 



ADX* 377. 



4-1 



Program II fhe Inchwom 



OCTAL EQUIVALENT 

977 760,, 400 023 

362 

3^ 51 00 377,751 

01 11 02 377,750 

02 11 03 377,750 
74 11 71 377,762 

40 20 71 377,763 
54 17 62 377,744 

41 15 02 377,744 

40 30 71 000,007 

41 771 377,756 
70 06 03 377,752 
41 11 02 377,761 
01 15 02 377,744 
01 30 00 000,005 
00 05 00 000,001 

This program 
001 



2 

3 
4 

5 
6 

7 



34 RSX 71 6 
°LDE 71 7 <- 



: SKN 3 ' 2 377,744 
: X ADX 2 377,744 
: °STE TX 16 
: Tl JNX 71 2 — - 
:" T JPX 3 377,752 



ADDRESS 
377 750 
751 
752 
753 
754 
755 
756 
757 
377 760 
761 
762 
763 
764 

765 
766 

377 767 



6M-5780 
SYMBOLIC 



6a 



last address,, 1st coiiSt 

config 34 set up 

II U 34 SPF 377,751 

J Li I, X RSX 2 377,750 

J^f^ 2 RSX 3 377,750 
34 RSX T1 377,762 

°LDE 71 377,763h 
SKN 3 * 2 e reg 

X ADX 2 e reg 

STE 71 000,007 

+1 JNX 71 377,756J 

" 7 JPX 3 restart 

[ I I : X RSX 2 377,761 

1 l I X STE 5 
JMP 1 



4/ 4/ 4/ n)/ 






then forms 

010 
11 
12 

13 
14 

15 
16 
and so on • . . 



this one 
: 34 RSX 71 15 

: °LDE 71 16 <L 

: SKN 3 « 2 377,744 
: X ADX 2 377,744 
: STE 71 25 

: +1 JNX 71 11 

:" 7 JPX 3 377,752 



J 



Program II The Inchworm 



6M-5780 7* 

The "flaw in the ointment" is that register 00£ will contain 
UOO,023 + 000,00? - 1*00,032 after the first mapping,, The STE 
instruction in 005 would have a deferred (indirect) reference to 
32 and this is clearly bad* It must be changed to a direct refer- 
ence to 016o This is accomplished by the ABX in 16$ which adds the 
000,007, which by then is in index register 2, to the 000,007 which 
remains in the right half of the E register (after the 1SX in 761*) 
resulting in an 000,016 in the E register* The STE in 766 puts it 
away into 00£ and the JMP transfers control to 001 continuing the 
process in core memory « 

Exercises To Prove To Yourself That You Really Understand 

Write a program which uses another approach to the problem of 
what to put in the 16 toggle switch registers to make core memory 
look as it does above „ 

Is it possible to use a JPX in 762 and, if so, what would the 
program look like then? 



6M-5780 8« 

IIIo Through the Looking Glass 
The Problem 

If all the registers in any block 'of memory registers were laid 
end to end, what program would put the mirror image of this mess 
back into the memory block? For example., if the block consisted of 
three U-bit words 9 the transformation would look like this? 

F l F 2 F 3 F h \ T 3 T 2 T l 

Si s 2 s 3 s^ J> % s : 



3 3 °2 



T i T 2 h T h F i* F 3 F 2 F : 






The Solution 

Program III*, which is written with floating addresses ^ performs 
this mirroring by the use of configurations and simultaneous cycling 
with only 20 instructions* 

Four unusual configurations are needed and these are set up in 
configuration memory locations 37 9 36 9 35 and 3I4. by the SPG instruc- 
tion o 

From some register containing the first and last addresses of 
the memory block*, the A register is set up and the w first* is put 
into the address section of the IDA instruction called M top 5 M and 
the "last" is put into the 'LDB called »boto w The general idea is 
to index through the block ^ taking a pair of words at a time and 
exchanging and reversing themo One word comes from the top half of 
the block and the other comes from the bottom half • If the block 
has an odd number of words in it, the first pair will be the middle 
word used twice , If the block has an even number of words s the first 
pair will be the middle two words. The last pair dealt with is al- 
ways the first and last words of the blocko 

Index register 8 contains a positive number which counts back 
from the middle of the block to the first o Index register 9 con- 
tains a negative number which counts up from the middle to the last* 
If there are 2n+2 or 2n+l words in the blocks index 8 starts out 
with +n and index 9 starts out with -n* These numbers are obtained 
from the first and last addresses after only two instructions « The 
first instruction is a SUB which subtracts , simultaneously ^ the last 
from the first and the first from the last I The left half of the 
A register then contains -(2n+l) for even blocks and -(2n) for odd 
blocks o The right half of A contains the complement of the left half o 



top=| 
t>ot=J 



<M 



6M-5780 



i 4 I i 34 SPG 1600,605,200, 

37 34 45 3* 



,i I I j. °LDA L£ : 
J>^<, a STA top 

. 1 \A I. l£5TA bot 

ail l, 3SsCA L*.--.i 

x 1 L4 i. X RSX 8 a reg 
2 RSX 8 a reg 
3e LDA 8 first 



3Stt\q9 



LDB 8 last 



RSX J 



J^v^LoLoL 3T ° AB 

uLiiirii^, 37 CYB 



'ifl = jLo = 1, 



£ *-£> ' 



+ 1 

I i i i °STA 

4* ^ vL >t STB 
+ x JNX 9 



again 



= p J* s> 



1,-1,-1,-1 

) 



L JPX @ top 



Done* halt or something, 



Program III Memory Mirror 



starts 



6M-5780 9a 



top=| 

bot=| 
agaln=| 



d=| 



vT^f^ 



J, J I I 34 SPG [600,605,200,202 

3 7 j f, 55 3 y. 

,i I I I, °LDA Lfirst^last 
.^>S<, 8STA *>P 

J_LoLi, 1STA bot 
viloLL 358 ^ L:i,-,-i,-- 

v I I A I. l nsx a a reg 
,>gg</RSX e a reg 

3a LDA 8 first ,<— —— 
^f^l 36 LDB 9 last 
RSX 1 |_^10 

uLiiiiA 37cy B 1^,2,2,2 I 

+ 1 JNX* again J 

iii li i 3 7CYA L:i , -i , -i , -i 
Miii. a7cYB Lii» -i,-i,-i 

J. J, J, 4,' °STA (top) 
4. I I I °STB (bot) 
+1 JNX S d 



-l 



'} 



JPX 8 top 



y 



Done, halt or somethings. 



Program III Memory Mirror 



6M-5Y80 10o 

The next instruction* SCA<» shifts each half one place to the 
rights leaving ~n in the left half and +n in the right half of A 
Index registers 8 and 9 are then set up from the appropriate half 
of Ao 

The basic iterative loop starts now and is executed n times „ 
The inner loop is executed 9 times for each of the n times through 
the outer loop. This number 9 is the number of bits in a quarter 
of a TX-2 word* If the reader wishes to work through an example 
with* let's say <> k bit quarters* then he should go through the inner 
loop four times * The index register (l) is preset to -8 however , 
since the JKX jumps on zero 

The STA and STB instructions (at d-3) have deferred addresses 
which they get from "top* and »bot« respectively o This is actually 
inefficient timewise if n is greater than 2o Two more instructions 
when setting up could have put direct references to "first 1 * and 
«last* in these STA and STB instructions . This would have cost h 
memory time cycles <> However * each deferred address costs one memory 
cycle and so 2n-U extra memory cycles are being executed in the basic 
loop. This illustrates how one can trade space for time or vice 
versao 

The two decimal numbers 8 and 9 were used to indicate general 
index registers* Of course* 1 is general too c 

Exercises To Prove To Yourself That You Beally Understand 

One need execute the inner loop only 8 times if a slightly 
different correction is made afterwards What are the new correct- 
ing cycle instructions? 

Configuration 35 is not really needed "What other one used by 
Program III would serve just as well? 



6M-5780 11 

IV* 50 Million Haiti plications Ca n't Be Wrong 
The Problem 

In the analysis of electro encephalography data 5 the autocorrela- 
tion function of the data is often desired (see Bo Go Farley } A 
specific useful example is the following s about £0 thousand samples 
are stored away in memory o Each sample is a sign and 8 bits (9 bits 
in all)o 

We wish to find 

i - 50,000 

for i=0 5 l^ oo ^1000 




where Sj is the j tb sample <, These 1000 numbers are proportional to 
the autocorrelation function*, 

The Solution 

Program IV computes this function in a most efficient way time- 
wise* The key to the speed is to do four multiplications simultane- 
ously* The data 5 however,, must be in memory in a particular format 9 
namely 

= s 1$ s 2$ s % s k 

1 S 2, s 3, %, B 5 

2 s 3, % S S, S 6 

3 % % % S 7 

h % % S 7, S 8 

5 % S 7, S 8, S 9 

Note that there are four of the 9 bit samples (Sj) in each 
TX-2 word and that registers B k^ etc and l s $ $ etCo will contain 
eight different successive samples 

The program starts out by setting up the four special configura- 
tions needed and reseting index register 8 to 2000 octal (about 1000 
decimal) o Index register 8 corresponds to the subscript i in the 
summation above* 



startH I I i I 34 SPG 11*2, 140,724,600 

27 3b 3,5 3^ 



e2=f 



6M~5?80 12, 



C M 4 I I i s°LBE L2 



4, J, I I °STE® 



W ii - 1 



RSX 9 Ll50,000 



Qtba® 



Ui I IiM 



lij^iii 



1X> *> 



3® 

37 



LL^JLZJ 



,^&, 



3® 



®TATmS 



J, >U J, °STA® 

" 4 JPX 9 c 




Done, display results (the 2000 sums 



Program 17 An Autocorrelation Program 



6M-5760 



starts ^ I i I 34 SPG \J&2 $ 140,72^,600 

17 3fc 3,5 3V- 

RSX 8 LJ!000 



12a- 



cH vl 4, J, I :°U>E L£ <" 



4, J, J, 4, °STE 8 sums 



4 1 X DPX 8 m 



RSX 9 |JL50,000 






si 4 I i °LDA e 000 4 



cbii.^ 34 MUL e ... index 8 ... 

X X 35exa b re « 



4, 4> 4, I °EXA 8 sums 



41 36 ADD b reg 



\#&>* 



37 



ADD b reg 



11 j 3e ADD 8 sums 



j^XN, 37 ADD 8 sums 



I si I ± °STA 8 sums 



-4tov9 



JPX* c2 



j 



-1 Tt>v8 



JPX° Cl 



Done, display results (the 2000 sums).. 



Program IV An .Autocorrelat ion Program 



6M-5780 13. 

The outer iterative loop then clears the i th current sum register 
and puts i into the address section of the MUL instruction at m* Index 
register 9 is set to 150*000 octal (about 50,000 decimal) . Index 9 
corresponds to the subscript j in the summationo This outer loop is 
executed about a thousand times „ 

The inner loop computes one complete summation (fixed i) taking 
four samples at a time* After the multiplication, the A and B regis- 
ters look like this; 

A = P^ 'P 2 , P 3 , P^ 

B " h.* ^2* L y L k 

where P is the most significant 9 bits of the product and I is the 
least significant o 

To eliminate round-off errors, the sums of each whole 18 bit pro- 
duct are accumulated,. To put the 9 bit pieces of the product together, 
the A register is exchanged with the B register in such a manner that 
the result looks like this: 

A . « P-l L-j_ ,, P^ I, 

B - P 2 H » \ \ 

These four 18 bit numbers are then added to the current sum which 
is a 36 bit number • Notice how the sign extension feature allows a 
signed 18 bit number to be added to a signed 36 bit number • 

Index register 9 is counted down by h ( il ) since only every fourth 
register of four samples need be multiplied* This means the inner loop 
is executed only about 13,000 times instead of 50,000 times* 

The whole program with its 50^000,000 multiplications will take 
8 minutes if the overlapped iremory feature is used (i e e if instructions 
and data are in different memories )o 

Bcercises T o Prove To Yourself That You Really Understand 

The data should extend to register 152,000* Why? 

Write a program^ using appropriate configurations (no shifting) 
and the TSD instruction^ which will read the samples into memory in the 
desired format. This program would operate in the Epsco Datrac (an 
analog-to-digital converter) sequence • Each TSD will put a signed 9 bit 
number into quarter 1 of the E register » Ignore In-Out Select instruc- 
tions o Nine instructions will do nicely 

Write a new inner loop to Program IV which handles data with only 
one sample per word* Five instructions including the JPX will do it. 
This inner loop will have to be executed the full 50 million times . 
How long will it take? 



6M-5780 UU< 



Vo The Flexo -Octal Converter 
The Problem 

In the beginning of a binary computers programming life, it is 
difficult to communicate with the machine o A series of programs must 
be written to "bootstrap* one*s way into easy communi cation « This 
bootstrap series might go like thiss 

First) A three (or so) word program in toggle switch storage 
which would allow words to be written into memory one at a time,, 
Call this PI. 

Second) A short routine to convert programs to binary which 
have been typed on a flexo in a rigid, simple, fixed- address format <> 
Call this P2o Associated with P2 is a program to punch out storage 
as a binary tape and a program to read in this binary tape<> PI loads 
P2 into memory o P2 converts the punch-out and read-in programs The 
punch-out program punches out P2, the read-in routine and itself « 
From now on, the read-in routine can read in P2 and the punch-out 
routine , eliminating the need for Plo 

Third) A longer routine which converts programs typed in a sym- 
bolic code., relative- address format* Call this P3o P2* converts P3 
and punches it out, eliminating the need for P2o 

Fourth) A routine to convert programs typed in a symbolic code^ 
floating address format (Pii) c ?k is written in P3 format and con- 
verted by P3 At this point PI, P2 or 1?3 aren*t needed any more and 
communication is fairly easy* In TX-O, PU was called T0DAL o A fifth 
stage might be an algebraic format converter like FCHTRANo 

Programs V, VI and VII are proposed examples of the second stage* 
The octal converter recognizes the eight flexo symbols 9 l s 2,3 9 h 9 $ 9 6 
and 7 takes their order into account „ Some control characters are 
needed, such as carriage return to signify the end of a word and 
slash to allow address specifications a The space 9 tab, and comma 
are used to give some format control* The nullify is recognized so 
that tape "goofs* can be fixed up c The last four are ignored by the 
converter o A stop code signifies the end-of-tape condition 

The Solution 

The program to do the octal conversion is Program V Q 

To decide what action to take on each character as it is read in, 
an Action Table is set up as is shown beside the program* An entry 
is made at the address, starting at 100, whose last 2 digits corres- 
pond to the flexo code of the appropriate character „ The right 18 
bits of each entry tell where to transfer control when that character 
is read in, and the left nine bits tell what the binary equivalent is 



ACTION TABLE 

- 0,0,000 201 



- 0*0*000 204 



113| =» 4*0*000 210 



2*0,000 210 



123| = 5,0*000 210 



1*0*000 210 



« 7*0*000 210 



1*5| - 0*0*000 204 
151f = 0*0*000 213 



6m-5?80 15. 

Description ROUTXUE 

200| * sJ0S 52 read unsplayed 



107| - 3,0*000 210 If slash-^- 201 |] 44/STA 213 



2ROY2 



RSX 2 105 



°TYDV© 



if ignored-^ 



I0S 52 dismiss^ 



206 



&T3Q Vl 



pU 



RSX 1 e reg 



O.TMPi 



JMP 1 (100) 



133| - 6*0*000 210 if number-* 210 .^4,44 °CYA 



211 y%L @ad ^ 1 ^00 



I6l| - 0*0*000 216 if ear/ret-^ 213 

1?6| * 0*0*000 210 214 

1771 - 0*0*000 204 215 



©am a 2 



&ATTV2 



UfUUtfa 



AUX 2 125 




if stop code«=^2l6 



I0S S2 shut off 



si « value *0* where to 



Program 7 The ' glexo-Octal Converter 



6M-5780 15a 

ACTION TABLE Description ROUTINE 

105| « 0,0,000 201 start at —> 200| « :IOS 52 read unsplayed 

107| » 3,0,000 210 If slash-^ 201 H^^STA 213 

110| « 0,0,000 204 202 /<^ 2 RSX 2 105 

H3| - 4,0,000 210 203 [N UxU, °DPX° a reg <-n 

117) « 2,0,000 210 If ignored^ 204 IOS 52 dismiss^ 

123| = 5,0,000 210 205 :TSD e reg 

125| - 1,0,000 210 206 If ] ^ 3 RSX 1 e reg 

1271 - 7,0,000 210 _>„,, 207 °JMP X (100) 

^%UU — - 

133| = 6,0,000 210 If numbers 210 f i4 4^ CYA 107 

1451 - 0,0,000 204 211 y%^ 6 ADD X 100 

151| = 0,0,000 213 212 JMP 204 _ 

l6l| - 0,0,000 216 If car/ret -> 213 lili °STA 2 memory 

176| = 0,0,000 210 214 7%C 6 AUX 2 125 

177| - 0,0,000 204 215 JMP 20 3 *> 

if stop code ~> 216 I0S 52 shut off 

address) = value, 0, where to go 

Program V The Flexo-O c tal C o nverter 



6M-5780 16o 

when the character is a' number o Quarter 3 of each entry is not used* 

The IGS in 200 sets the mode of the PETE to read one contiguous 
6-bit flexo code (unsplayed) into the right 6 bits of the E register, 
clearing the other 3 bits in that quarter ♦ 

Starting at 203 with a DPX which clears the A register, the char- 
acter is read in and placed in index register 1 The JMP then defers 
control to a location specified by the appropriate Action Table entry c 
Hote that all instructions with deferred addresses are indexable o 

If the character is a number,, then control goes to 210 where the 
A register is cycled left 3 places and the binary equivalent of the 
number is added into A 5 returning control to 20lio 

If the character is a slash 3 control ^bounces off* register 105 
to register 201 where the number in A is stored in 213 and index 
register 2 reset to a zero* The slash then causes the number that 
has been built up in A to be the new address of the word which follows * 

If the character is a carriage return^ 213 has control and stores 
the word in A away in the proper memory location „ The AU& in 211; adds 
a 1 to index register 2 so that the next time a carriage return appears, 
the word in A will be stored in the memory register following the last 
onee 

The nullify s space a and tab simply return control to 20ij to read- 
in the next character. When a stop code comes along, the IOS in 216 
shuts off the photo reader and dismisses the sequence e 

The sequence must be dismissed after each character is read and 
the IOS in 20U does this* The TSD in 205 empties a buffer that has 
been filled by the PETRo Mien the buffer is filled, the sequence is 
activated and the character read-in is dealt with* 

Exercises To Prove To Yourself That You Really Understand 

What are the implications of throwing out the 105 in 201* and 
not holding on the TSD which follows? In other words, let the TSD 
dismiss the sequence after transferring the data Q Work out the new 
program and format rule(s ) Q 

The instructions in 210-11 are on rather shaky ground because 
TX-2 is an allegedly multi -sequence machine o Some lower priority 
sequence may have been using the A register and will be very upset 
at finding it disturbed,, What changes will fix this up? Don't for- 
get 203 n 

Is there anything fishy about the 2SX in 206? 



6M-5780 17. 

VIo A Binary Read- In Routine 

The Problem 

In one of its modes 9 the photoreader reads the six bits of a 
line of tape into every sixth bit of some specified word and cycles 
the word left one place . This is the "splayed** mode of the photo- 
reader sequence. After reading in six lines $ a full 36 bit word is 
assembled* This mode would usually be used to read in binary tapes . 

The main problem associated with a binary read-in routine is 
what format to use* In general <> data words are read into blocks of 
consecutive memory registers and three provisions are madej (1) to 
read in more than one blocks (2) to check the sum of each block thereby 
detecting almost any error s (3) to specify what should happen to con- 
trol after all blocks are read in„ 

The Solution 

Program VI uses the following format for each block of binary 
words g 

-n 99 last address 
Word 
Word 1 



Word n 
more? 9S = sum 

The first word in each block consists of two 18 bit numbers (see 
instructions at 3 and h) which designate the addresses of the actual 
data words which f ollowo 

The right half of the last word is the complement of the sum of 
all the other half words in the blocko In other words 9 if all the 
words in a block are added up in 18 bit pieces (ins true tionTat 2k 
and 25) the sum must be zero (instructions at 12 and 13) or there has 
been an error. If there is an error 5, the tape is backed up (instruc- 
tion I?) and read in again, (TX=2 5 as you may have guessed by now, 
can read paper tape in either direction and can identify the front of 
the tape*.) 

The sign bit (k*9) of the left half of the last word in a block 
tells whether there are more (if lu9 is a ONE) blocks to be read in 
or not (if k°9 is a ZERO, see instruction 110 . If there are more 



oof 



6M-5780 18. 



8i 



W 1 



IOS 52 read forward, splayed, dismiss 
RSX 3 26 * 



°ct 



2 Vave" 2j M p* 21 



^ 3 u^S, :8Rsxa 30 




^ 



% 



L STE 07 



«* 



5 'la^ve" 



14 \ 



P(y^ 6 t4l4°>° 



D A 1 Uli °STE 2 last 



10 + 1 JNX 2 5 

11 "auve" 2 JMP 4 2: 



J 



C. 12 



r, 



13 



+ °JPX 3 17— 



>S> 1* 



><> 



/V 



SKZ 4»S 3Q 



15 



0. 



'*, 



'^16 



SUB-ROUTINE 
TO READ 6 LINES 

22 TSD 30 <-| 

I 
i 

23 _1 JPX 1 22 
2^ t £^§C J 2 AUX 3 30 
25 1 M. I iX 1 AUX 3 30 



.26 'k*i.*x X JMP* 000 



0,0,0,5 
read in 




G 17 
0. 



'0 



I0S 2 baek up tape, dismiss 



'/> 



Program 71 A Binary Read-In Routine 



to 



00| 



tv 1 



6M-5780 
IOS 52 read forward, splayed, dismiss 

RSX 3 26 * 



18a 



£<, 



'Q 



2 "n«" S JMP 4 21 



^£ r 3 ,^5^ : 8 RSX 2 30 
Rfi 4f, 



4 / I J4 X STE 07 




5 Adve" Z JMP* 21 



*1 



A 



P, 6 ^^ :°LDE 30 
D A^ 7 ^44 °STE 2 last 



10 +1 JNX 2 5 

11 'Wve" 2 JMP 4 21 



C, 12 



r. 



13 



^ 



^ i* 



>^> 



*i 



15 



+°JPX 3 17- 
+ °JNX 3 17 ~> 
SKZ 4 - 9 30 
JMP 1 *, 



SUB-ROUTINE 
TO READ 6 LINES 



TSD 30 <-j 



21| - ( l^ i U i 1 RSX 1 27 
22 

23 " 1 JPX i 22 -J 

24 ^^^/AUX 3 30 

25 ^i^/AUX 3 30 

26 "l*d*y* *JMP 4 000 



27 



30 



0,0,0,5 



word read in 



l 



£> 



'*, 



^ 16 



J 



IOS 5Z shut off, dismiss 



G„ 17 

V 

20 



I0S 52 back up tape, dismiss 
JMP 000 



Program VI A Binary Read-in Routine 



6M-5780 19. 

blocks^ control goes to register 1 and reads in the next block* pro- 
viding of course that there were no check sum errors « If there are 
no more blocks,, instruction 16 shuts off the PETB and dismisses the 
sequence <, 

Exercises To Prove To Yourself That You Really Understand 

Note that there is no provision made in the tape format of 
Program VI for turning on any other sequence after the last block has 
been read in. There is really no necessity for a control change since 
the Start-Over sequence can start up the program just read in at the 
poke of a button „ 

However 9 pay homage to the (W„ A ) Clarkian philosophy of minimal 
button poking and make the necessary additions of Program VI and its 
format which will start the program in sequence #S at a register called 
START if bit Uo8 of the last word in the last block is a ONE* If lu8 
is a ZERO, make Program VI do what it does now This addition can 
be accomplished with eleven more words (maybe fewer)* 

Why are the CF bits of instruction 12 all ZEROS? 

Bo they need to be ZEROS in instruction 13? Miy? 



6M-5780 20< 



VII c A Punch Out Routine 

To prove to yourself that you really ^ really understand^ write 
a program to punch out storage in the block format required by the 
read in routine (VI) Control it from a toggle switch register in 
the following manners 

Let the left half of the toggle switch register be 
the first address* and the right half,, the last address 
of the block to be punched out* 

Let the meta bit (lulO) designate whether this is 
the last block or noto 

Let bit l*o 9 be a ONE when the toggles are being 
changed^ and a ££R0 when the program can look at the 
register „ 

The author has written this program with 33 instructions The 
best solution submitted by a reader 9 will be published in a supple- 
ment to this memo* 



CONCLUDING EBMARKS 

The six programs in this memo illustrate many of the characteristics 
of TX-2* There are other features which haven »t been illustrated <, For 
example j conditionally saving the P and/or Q register in E after a JKP) 
using multiple step deferred (indirect) addresses § using the Boolean 
instructions or the skip if E is different from word instructions using 
the operate class commands and many sequences operating simultaneously 

There will be supplements to this memo from time to time which illus- 
trate features such as those mentioned in the preceding paragraph*. Any 
suggestions^ improvements^ discoveries^ or remarks in general will be 
appreciated by the author and probably also by his associates 

HPP/mk 

Insertions s 



9a 
12a 
15a 
18a 



6M-5780 21< 



notes